/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "brcm,bcm6345";

	aliases {
		pflash = &pflash;
		serial0 = &uart0;
		gpio0 = &gpio0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "brcm,bmips32", "mips,mips4Kc";
			device_type = "cpu";
			reg = <0>;
		};
	};

	cpu_intc: interrupt-controller {
		#address-cells = <0>;
		compatible = "mti,cpu-interrupt-controller";

		interrupt-controller;
		#interrupt-cells = <1>;
	};

	memory { device_type = "memory"; reg = <0 0>; };

	pflash: nor@1fc00000 {
		compatible = "cfi-flash";
		reg = <0x1fc00000 0x400000>;
		bank-width = <2>;
		#address-cells = <1>;
		#size-cells = <1>;

		status = "disabled";
	};

	ubus@fff00000 {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		periph_intc: interrupt-controller@fffe000c {
			compatible = "brcm,bcm6345-l1-intc";
			reg = <0xfffe000c 0x9>;

			interrupt-controller;
			#interrupt-cells = <1>;

			interrupt-parent = <&cpu_intc>;
			interrupts = <2>;
		};

		ext_intc: interrupt-controller@fffe0014 {
			compatible = "brcm,bcm6345-ext-intc";
			reg = <0xfffe0014 0x4>;

			interrupt-controller;
			#interrupt-cells = <2>;

			interrupt-parent = <&cpu_intc>;
			interrupts = <3>, <4>, <5>, <6>;
		};

		uart0: serial@fffe0300 {
			compatible = "brcm,bcm6345-uart";
			reg = <0xfffe0300 0x18>;

			interrupt-parent = <&periph_intc>;
			interrupts = <2>;

			/* clocks = <&periph_clk>; */
			/* clock-names = "refclk"; */

			status = "disabled";
		};

		gpio0: gpio-controller@fffe0404 {
			compatible = "brcm,bcm6345-gpio";
			reg = <0xfffe0404 4>, <0xfffe0408 4>;

			gpio-controller;
			#gpio-cells = <2>;

			ngpios = <16>;
		};
	};
};
